In microelectronics, multigate devices such as trigate, finfet, nanowires, and nanotubes have been promising for device scaling due to superior electrostatics. However, these devices are more prone to parasitic resistance due to the extremely thin Si or carbon (C) body or III-V body (less than 20 nm) and current crowding with the 3-dimensional architectures. In order to reduce the parasitic resistance and also to enable contact, these thin Si bodies (fins, wires, or cubes) are usually merged with epitaxial (epi) Si or SiGe(C) that is heavily doped by in situ doping and/or ion implantation, like the conventional source/drain areas, and then silicided.
However, epitaxial deposition is a complex and expensive process. In particular, it is challenging to achieve epi uniform on NFETs and PNFET, and across the wafer. Moreover, the pre-epi cleans and epitaxial growth conditions are very sensitive to the dopant species, and their concentration at the re-growth interface requires extensive optimization. In addition, the epi process requires a capping layer on the poly gate (or poly or a-Si portion of high-k metal gates), which requires additional process steps and significantly constrains the device design and process integration.
In the method of the disclosure, a metallic film is selectively deposited on top of a source/drain and gate regions using an electroless deposition technique, in which parasitic external resistance is decreased. This approach is completely compatible with conventional high performance CMOS flows, and eliminates the added complexity and cost of a conventional epi RSD process.